38. Chip Select Expansion

Solution Explanation

• Output Select Analysis: Because the outputs are active-low, only one selected output drops to 0 when its specific address matches, while the other three stay at 1. For example, Y0 becomes 0 only when both inputs are 0.
• Hardware Optimization: The circuit splits the main inputs into inverted paths using NOT gates. These original and inverted lines connect directly to four separate NAND gates, ensuring that exactly one device is selected at a time without any overlap.

Boolean Equations:

• Y0 = ~(~A1 . ~A0)
• Y1 = ~(~A1 . A0)
• Y2 = ~(A1 . ~A0)
• Y3 = ~(A1 . A0)