9. Parity Bit Generator

Implement a 3-input parity generator circuit that matches the provided behavioral reference. Your goal is to optimize the circuit layout to achieve the absolute minimum component footprint possible.

Constraints

  • You must utilize three input sources: A, B, and C.
  • The circuit must generate an odd parity bit (Output high if the number of high inputs is odd).
  • Standard NOT, AND, or OR gates are prohibited for this optimization challenge.
  • Your complete circuit implementation must contain a maximum of 2 total logic gates.

Behavioral Reference

ABCOutput
0000
0011
0101
0110
1001
1010
1100
1111