Testbench Code
`timescale 1ns/1ps
module tb_decoder3to8;
// 1) Inputs
reg [2:0] s;
// 2) DUT outputs
wire [7:0] y;
// 3) Expected (purely combinational from inputs)
wire [7:0] expected_y = (8'b0000_0001 << s);
// 4) Single mismatch flag (case-inequality catches X/Z differences)
wire mismatch = (y !== expected_y);
// Accounting
integer TOTAL_TEST_CASES = 0;
integer TOTAL_PASSED_TEST_CASES = 0;
integer TOTAL_FAILED_TEST_CASES = 0;
// Limits
integer VCD_MAX_CASES = 64; // normal rows printed
integer ERROR_MAX_CASES = 64; // error rows printed
integer printed_rows = 0;
integer printed_errors = 0;
// DUT (pick one implementation)
decoder3to8 dut(.s(s), .y(y));
// VCD dump
initial begin
$dumpfile("tb_decoder3to8.vcd");
$dumpvars(0,
tb_decoder3to8.s,
tb_decoder3to8.y,
tb_decoder3to8.expected_y,
tb_decoder3to8.mismatch
);
$dumpon;
end
// Header + init
initial begin
s = 3'b000;
$display(" s | y | expected_y | mismatch");
$display("---------------------------------------------------");
end
// Apply + check (drive -> wait -> read combinational mismatch)
task apply_and_check;
input [2:0] ts;
begin
s = ts;
#1; // settle
TOTAL_TEST_CASES = TOTAL_TEST_CASES + 1;
if (!mismatch) begin
TOTAL_PASSED_TEST_CASES = TOTAL_PASSED_TEST_CASES + 1;
if (printed_rows < VCD_MAX_CASES) begin
$display(" %0d | 0x%02h | 0x%02h | %0d",
s, y, expected_y, mismatch);
printed_rows = printed_rows + 1;
end
end else begin
TOTAL_FAILED_TEST_CASES = TOTAL_FAILED_TEST_CASES + 1;
if (printed_errors < ERROR_MAX_CASES) begin
$display("ERR: s=%0d => y=0x%02h (expected 0x%02h)",
s, y, expected_y);
printed_errors = printed_errors + 1;
end
end
// Optional: stop VCD after cap of total vectors
if (TOTAL_TEST_CASES == VCD_MAX_CASES) $dumpoff;
end
endtask
integer i;
initial begin
// Exhaustive over valid 0..7
for (i = 0; i < 8; i = i + 1)
apply_and_check(i[2:0]);
// Summary
$display("---------------------------------------------------");
$display("TOTAL_TEST_CASES=%0d", TOTAL_TEST_CASES);
$display("TOTAL_PASSED_TEST_CASES=%0d", TOTAL_PASSED_TEST_CASES);
$display("TOTAL_FAILED_TEST_CASES=%0d", TOTAL_FAILED_TEST_CASES);
$display("ALL_TEST_CASES_PASSED=%s", (TOTAL_FAILED_TEST_CASES==0) ? "true" : "false");
#2 $finish;
end
endmodule