55. Demultiplexer

A. Dataflow one-linermodule demux1to4 (
    input       d,
    input [1:0] s,
    output [3:0] y
);
    // One-hot mask (1 << s), then gate with d replicated across 4 bits.
    assign y = ({4{d}}) & (4'b0001 << s);
endmodule
B. Equivalent case version (Behavioral)module demux1to4 (
    input       d,
    input [1:0] s,
    output reg [3:0] y
);
    always @* begin
        y = 4'b0000;
        case (s)
            2'b00: y[0] = d;
            2'b01: y[1] = d;
            2'b10: y[2] = d;
            2'b11: y[3] = d;
        endcase
    end
endmodule
💡Remember
({4{d}} & (1 << s)) builds a one-hot at index s and drives it with d.
With always @*, always give defaults to avoid unintended latches.
If you want X/Z-detecting select handling, use casez and decide what to drive on unknowns (often y = 4'bxxxx;); beginners can stick with plain case and clean inputs.

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Testbench Code

`timescale 1ns/1ps

module tb_demux1to4;
    // 1) Inputs
    reg        d;
    reg  [1:0] s;

    // 2) DUT outputs
    wire [3:0] y;

    // 3) Expected (purely combinational from inputs)
    wire [3:0] expected_y = ({4{d}}) & (4'b0001 << s);

    // 4) Single mismatch flag (case-inequality catches X/Z differences)
    wire mismatch = (y !== expected_y);

    // Accounting
    integer TOTAL_TEST_CASES        = 0;
    integer TOTAL_PASSED_TEST_CASES = 0;
    integer TOTAL_FAILED_TEST_CASES = 0;

    // Limits
    integer VCD_MAX_CASES   = 64; // normal rows printed
    integer ERROR_MAX_CASES = 64; // error rows printed
    integer printed_rows    = 0;
    integer printed_errors  = 0;

    // DUT (use either dataflow or case implementation)
    demux1to4 dut(.d(d), .s(s), .y(y));

    // VCD dump
    initial begin
        $dumpfile("tb_demux1to4.vcd");
        $dumpvars(0,
            tb_demux1to4.d,
            tb_demux1to4.s,
            tb_demux1to4.y,
            tb_demux1to4.expected_y,
            tb_demux1to4.mismatch
        );
        $dumpon;
    end

    // Header + init
    initial begin
        d = 1'b0; s = 2'b00;
        $display(" d  s |   y    | expected_y | mismatch");
        $display("--------------------------------------");
    end

    // Apply + check (drive -> wait -> read combinational mismatch)
    task apply_and_check;
        input       td;
        input [1:0] ts;
        begin
            d = td; s = ts;
            #1; // settle

            TOTAL_TEST_CASES = TOTAL_TEST_CASES + 1;
            if (!mismatch) begin
                TOTAL_PASSED_TEST_CASES = TOTAL_PASSED_TEST_CASES + 1;
                if (printed_rows < VCD_MAX_CASES) begin
                    $display(" %0d  %0d | 0x%1h  |    0x%1h    |    %0d",
                             d, s, y, expected_y, mismatch);
                    printed_rows = printed_rows + 1;
                end
            end else begin
                TOTAL_FAILED_TEST_CASES = TOTAL_FAILED_TEST_CASES + 1;
                if (printed_errors < ERROR_MAX_CASES) begin
                    $display("ERR: d=%0d s=%0d => y=0x%1h (expected 0x%1h)",
                             d, s, y, expected_y);
                    printed_errors = printed_errors + 1;
                end
            end

            // Optional: stop VCD after cap of total vectors
            if (TOTAL_TEST_CASES == VCD_MAX_CASES) $dumpoff;
        end
    endtask

    integer i;
    initial begin
        // Directed: all selects with d=0 then d=1
        for (i = 0; i < 4; i = i + 1) apply_and_check(1'b0, i[1:0]);
        for (i = 0; i < 4; i = i + 1) apply_and_check(1'b1, i[1:0]);


        // Summary
        $display("--------------------------------------");
        $display("TOTAL_TEST_CASES=%0d", TOTAL_TEST_CASES);
        $display("TOTAL_PASSED_TEST_CASES=%0d", TOTAL_PASSED_TEST_CASES);
        $display("TOTAL_FAILED_TEST_CASES=%0d", TOTAL_FAILED_TEST_CASES);
        $display("ALL_TEST_CASES_PASSED=%s", (TOTAL_FAILED_TEST_CASES==0) ? "true" : "false");

        #2 $finish;
    end
endmodule