/*Write your code here*/
module demux1to4(input [1:0]s,input d,output [3:0]y);
wire not_s1,not_s0;
not n1(not_s1,s[1]);
not n0(not_s0,s[0]);
and a0(y[0],not_s0,not_s1,d);
and a1(y[1],s[0],not_s1,d);
and a2(y[2],not_s0,s[1],d);
and a3(y[3],s[0],s[1],d);
endmodule