66. Demultiplexer

How do you plan to solve it?

/*Write your code here*/
module demux1to4(input d , input [1:0]s , output reg [3:0]y);

    //assign y = ({4{d}}) & (4'b0001 << s);
    always @(*) begin
        y = 4'b0000;
        
        case(s)
            2'b00 : y[0] = d;
            2'b01 : y[1] = d;
            2'b10 : y[2] = d;
            2'b11 : y[3] = d;
        endcase


    end


endmodule