How do you plan to solve it?
/*Write your code here*/ module demux1to4(d,s,y); input wire d; input wire [1:0] s; output wire [3:0] y; assign y[0]=(~s[1])&(~s[0])&d; assign y[1]=(~s[1])&(s[0])&d; assign y[2]=(s[1])&(~s[0])&d; assign y[3]=(s[1])&(s[0])&d; endmodule