34. Equality Operators

module x_detector (
    input  [1:0] a,
    output       eq_logic,
    output       eq_case
);
    assign eq_logic = (a == 2'bx1);   // logical equality
    assign eq_case  = (a === 2'bx1);  // case equality
endmodule
💡Remember
== / != → logical equality: if any bit is x/z, result = x.
=== / !== → case equality: compares all 4 states literally (0,1,x,z).
Use === when you really need to detect unknown/high-Z explicitly in simulation.

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Testbench Code

`timescale 1ns/1ps

module tb_x_detector;
    // 1) Inputs
    reg [1:0] a;

    // 2) DUT outputs
    wire eq_logic;
    wire eq_case;

    // 3) Expected
    reg expected_eq_logic;
    reg expected_eq_case;

    // 4) Mismatch
    wire mismatch = (eq_logic !== expected_eq_logic) || (eq_case !== expected_eq_case);

    // Counters
    integer TOTAL_TEST_CASES=0, TOTAL_PASSED_TEST_CASES=0, TOTAL_FAILED_TEST_CASES=0;
    integer VCD_MAX_CASES = 32;

    // DUT
    x_detector dut(.a(a), .eq_logic(eq_logic), .eq_case(eq_case));

    // VCD dump (Inputs -> Outputs -> Expected -> Mismatch)
    initial begin
        $dumpfile("tb_x_detector.vcd");
        $dumpvars(0,
            tb_x_detector.a,                  // Inputs
            tb_x_detector.eq_logic, tb_x_detector.eq_case, // Outputs
            tb_x_detector.expected_eq_logic, tb_x_detector.expected_eq_case, // Expected
            tb_x_detector.mismatch            // Mismatch
        );
        $dumpon;
    end

    // Apply + check
    task apply_and_check;
        input [1:0] ta;
        begin
            a = ta;
            expected_eq_logic = (a ==  2'bx1);
            expected_eq_case  = (a === 2'bx1);

            #1;
            TOTAL_TEST_CASES++;
            if (!mismatch) TOTAL_PASSED_TEST_CASES++;
            else           TOTAL_FAILED_TEST_CASES++;

            $display("a=%b | eq_logic=%b (exp=%b) | eq_case=%b (exp=%b) | mismatch=%0d",
                     a, eq_logic, expected_eq_logic, eq_case, expected_eq_case, mismatch);

            if (TOTAL_TEST_CASES == VCD_MAX_CASES) $dumpoff;
        end
    endtask

    initial begin
        $display(" a  | eq_logic | eq_case | mismatch");
        $display("-----------------------------------");

        // Directed cases
        apply_and_check(2'b00);
        apply_and_check(2'b01);
        apply_and_check(2'b10);
        apply_and_check(2'b11);
        apply_and_check(2'bx0);
        apply_and_check(2'bx1);
        apply_and_check(2'bz1);

        // Summary
        $display("-----------------------------------");
        $display("TOTAL_TEST_CASES=%0d", TOTAL_TEST_CASES);
        $display("TOTAL_PASSED_TEST_CASES=%0d", TOTAL_PASSED_TEST_CASES);
        $display("TOTAL_FAILED_TEST_CASES=%0d", TOTAL_FAILED_TEST_CASES);
        $display("ALL_TEST_CASES_PASSED=%s",
                 (TOTAL_FAILED_TEST_CASES==0) ? "true" : "false");

        #2 $finish;
    end
endmodule