How do you plan to solve it?
module x_detector ( input [1:0] a, output eq_logic, output reg eq_case ); // TODO: implement both comparisons assign eq_logic = a == 2'bx1; always @(*) begin case(a) 2'bx1 : eq_case = 1'b1; default : eq_case = 1'b0; endcase end endmodule