Fan-Out Wire

September 29, 2025

Solving Approach

How do you plan to solve it?

Fan-out limitations are typically not modeled in HDL simulations because they are physical implementation concerns related to signal loading and drive strength. These effects are handled during synthesis and physical design, not during RTL simulation.

Code

module top_module(
    // Declare Inputs and outputs here
    input a,
    output y1,
    output y2,
    output y3
);
    // Module functionality here
    assign y1 = a;
    assign y2 = a;
    assign y3 = a;

endmodule

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Testbench Code

`timescale 1ns/1ps

module tb;
  // Inputs
  reg a;
  // Outputs
  wire y1, y2, y3;
  // Expected Outputs
  reg expected_y1, expected_y2, expected_y3;

  // Mismatch signal (high if any output mismatches expected)
  wire mismatch = (y1 !== expected_y1) ||
                  (y2 !== expected_y2) ||
                  (y3 !== expected_y3);

  // DUT
  top_module dut(.a(a), .y1(y1), .y2(y2), .y3(y3));

  integer TOTAL, PASS, FAIL;

  initial begin
    $dumpfile("tb.vcd");
    // VCD: inputs -> outputs -> expected -> mismatch
    $dumpvars(0,
      tb.a,
      tb.y1, tb.y2, tb.y3,
      tb.expected_y1, tb.expected_y2, tb.expected_y3,
      tb.mismatch
    );

    TOTAL=0; PASS=0; FAIL=0;

    // a=0
    a=0; expected_y1=0; expected_y2=0; expected_y3=0; #5;
    TOTAL++;
    if (!mismatch) PASS++; else FAIL++;
    $display("a=%b | y1=%b y2=%b y3=%b | exp_y1=%b exp_y2=%b exp_y3=%b | mismatch=%b",
              a, y1, y2, y3, expected_y1, expected_y2, expected_y3, mismatch);

    // a=1
    a=1; expected_y1=1; expected_y2=1; expected_y3=1; #5;
    TOTAL++;
    if (!mismatch) PASS++; else FAIL++;
    $display("a=%b | y1=%b y2=%b y3=%b | exp_y1=%b exp_y2=%b exp_y3=%b | mismatch=%b",
              a, y1, y2, y3, expected_y1, expected_y2, expected_y3, mismatch);

    // Summary
    $display("======================================");
    $display("TOTAL_TEST_CASES=%0d", TOTAL);
    $display("TOTAL_PASSED_TEST_CASES=%0d", PASS);
    $display("TOTAL_FAILED_TEST_CASES=%0d", FAIL);
    $display("ALL_TEST_CASES_PASSED=%s", (FAIL==0)?"true":"false");
    $display("======================================");
    $finish;
  end
endmodule