2. Fan-Out Wire

How do you plan to solve it?

Fan-out limitations are typically not modeled in HDL simulations because they are physical implementation concerns related to signal loading and drive strength. These effects are handled during synthesis and physical design, not during RTL simulation.

module top_module(
    // Declare Inputs and outputs here
    input a,
    output y1,
    output y2,
    output y3
);
    // Module functionality here
    assign y1 = a;
    assign y2 = a;
    assign y3 = a;

endmodule