75. D Latch

Design a level-sensitive D latch. When EN=1, the output must follow D. When EN=0, the latch must hold its previous value.

Requirements

• Module: d_latch
• Ports:
  • Inputs:
    • EN
    • D
  • Outputs:
    • Q
• Functional behavior
  • EN=1 → Q tracks D
  • EN=0 → Q holds previous value
  • No internal reset; any initialization is driven by stimulus
• Modeling constraints
  • Infer a level-sensitive latch using always @(EN or D) (or always @(*)).
  • Use nonblocking assignments (<=) for storage.
  • Ensure no assignments occur in the hold path so the latch retains state.

Behaviour / Worked Example

Starting from Q=0:

1. EN=1, D=0 → Q=0
2. EN=1, D=1 → Q=1
3. EN=0, D=0 → Q=1 (hold)
4. EN=0, D=1 → Q=1 (hold)
5. EN=1, D=0 → Q=0