82. JK Flip-Flop with Enable

Design a positive-edge–triggered JK flip-flop that responds to J/K only when EN=1; otherwise, it holds its state.

Requirements

• Module: jk_ff_enable
• Ports:
  • Inputs:
    • CLK
    • EN
    • J
    • K
  • Outputs:
    • Q
• Functional Behavior
  • On posedge CLK with EN=0 → hold
  • On posedge CLK with EN=1 → apply JK truth table:
    • J=0,K=0 → hold
    • J=0,K=1 → reset (Q=0)
    • J=1,K=0 → set (Q=1)
    • J=1,K=1 → toggle (Q=~Q)
  • Between edges → hold
• Modeling constraints
  • Implement with always @(posedge CLK); guard JK logic behind EN.
  • Use nonblocking assignments (<=).