83. T Flip-Flop

Design a positive-edge–triggered T flip-flop that toggles on each rising edge when T=1 and holds when T=0.

Module: t_ff
Ports:
- Inputs:
  - CLK
  - T
- Outputs:
  - Q
Functional behavior
- On posedge CLK with T=0 → hold
- On posedge CLK with T=1 → toggle (Q=~Q)
- Between edges → hold
Modeling constraints
- Implement with always @(posedge CLK) and nonblocking assignments (<=)