81. JK Flip-Flop

Design a positive-edge–triggered JK flip-flop implementing the standard hold, reset, set, and toggle behaviors.

Module: jk_ff
Ports:
- Inputs:
  - CLK
  - J
  - K
- Outputs:
  - Q
Behavior
- On CLK ↑ with J=0,K=0 → hold
- On CLK ↑ with J=0,K=1 → reset (Q=0)
- On CLK ↑ with J=1,K=0 → set (Q=1)
- On CLK ↑ with J=1,K=1 → toggle (Q=~Q)
- Between rising edges → hold
Modeling constraints
- Implement with always @(posedge CLK) and nonblocking assignments (<=).