module led_toggle (
input clk,
output reg led
);
initial led = 1'b0;
always @(posedge clk) begin
led <= ~led; // toggle at each rising edge
end
endmodule
đź’ˇRemember
always @(posedge clk) describes logic that updates once per rising clock edge.- Outputs driven inside such a block remember their value from one edge to the next.
- Using
<= (non-blocking) ensures all sequential updates happen in parallel at each clock. - Here, the LED simply toggles (
0→1→0→1...) every clock cycle, because we assign led <= ~led;. - In hardware terms this becomes a 1-bit storage element, but you can just think:
“on each clock tick, update LED to the opposite of its current value.”