Design an 8-bit logical shifter that outputs both the left-shifted and right-shifted versions of its input by a variable amount.
Requirements
- Module name:
shift8 - Inputs:
A[7:0] — data to shiftshamt[2:0] — shift amount (0–7)
- Outputs:
SHL[7:0] — logical left shift, A << shamtSHR[7:0] — logical right shift, A >> shamt
Notes
- Use logical shifts only (
<<, >>). - Vacated bits must be filled with 0; bits shifted out are discarded.
- If
shamt = 0, then SHL = SHR = A.
Worked examples
For A = 8'b1010_1100 (0xAC):
shamt | SHL (A << shamt) | SHR (A >> shamt) |
|---|
| 0 | 1010_1100 | 1010_1100 |
| 1 | 0101_1000 | 0101_0110 |
| 3 | 0110_0000 | 0001_0101 |
| 7 | 0000_0000 | 0000_0001 |