14. Logical Shifter

module shift8 (
    input  [7:0] A,
    input  [2:0] shamt,
    output [7:0] SHL,
    output [7:0] SHR
);
    assign SHL = A << shamt;  // logical left shift (zeros into LSBs)
    assign SHR = A >> shamt;  // logical right shift (zeros into MSBs)
endmodule

💡Remember

Logical shifts insert 0s; they don’t preserve sign.
Output width equals the left operand’s width (8 bits here).
Shifting by 0 is a pass-through; shifting by 7 leaves at most one bit.