14. Logical Shifter

How do you plan to solve it?

module shift8(
    input [7:0] A,
    input [2:0] shamt,
    output [7:0] SHL,
    output [7:0] SHR
);
assign SHL = (shamt == 3'd0) ? A : (A << shamt);
    assign SHR = (shamt == 3'd0) ? A : (A >> shamt);
endmodule