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14. Logical Shifter

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Solving Approach

How do you plan to solve it?

  • Use built-in Verilog shift operators for simple, clean logic.
  • Shift left (<<) to produce SHL and shift right (>>) for SHR.
  • Use 3-bit shamt to allow shifts from 0 to 7 bits.
  • Purely combinational logic—no always blocks needed.
  • Ensures variable-amount shifting with minimal hardware.

Code

/*Write your code here*/
module shift8(
    input [7:0] A,
    input [2:0] shamt,
    output [7:0] SHL,
    output [7:0] SHR
);
    assign SHL = A<<shamt;
    assign SHR = A>>shamt;
endmodule

 

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