14. Logical Shifter

How do you plan to solve it?

/*Write your code here*/

module shift8(A,shamt,SHL,SHR);

input [7:0]A;
input [2:0]shamt;

output reg [7:0]SHL;
output reg [7:0]SHR;

always@(*)begin
        SHL=A<<shamt;
        SHR=A>>shamt;
end

endmodule