14. Logical Shifter

How do you plan to solve it?

module shift8(
    input [7:0] A,
    input [2:0] shamt,
    output [7:0] SHL,
    output [7:0] SHR 
);

assign SHL = A[7:0] << shamt[2:0] ;
assign SHR = A[7:0] >> shamt[2:0] ;

endmodule