module shift8 (
input [7:0] A,
input [2:0] shamt, // shift amount (0–7) it has 3 bits which rep values till 7
output [7:0] SHL,
output [7:0] SHR
);
assign SHL = A << shamt; // logical left shift
assign SHR = A >> shamt; // logical right shift
endmodule