14. Logical Shifter

How do you plan to solve it?

/*Write your code here*/
module shift8
(
input wire [7:0] A, input wire [2:0] shamt,
output reg [7:0] SHL,SHR
);
always@*
begin
    case(shamt)
    3'd0:
        begin
            SHL=A;
            SHR=A;
        end
    3'd1:        
        begin
            SHL=A<<1;
            SHR=A>>1;
        end
    3'd2:        
        begin
            SHL=A<<2;
            SHR=A>>2;
        end
    3'd3:        
        begin
            SHL=A<<3;
            SHR=A>>3;
        end
    3'd4:
        begin
            SHL=A<<4;
            SHR=A>>4;
        end
    3'd5:        
        begin
            SHL=A<<5;
            SHR=A>>5;
        end
    3'd6:        
        begin
            SHL=A<<6;
            SHR=A>>6;
        end
    3'd7:
        begin
            SHL=A<<7;
            SHR=A>>7;
        end
    endcase
end
endmodule