14. Logical Shifter

How do you plan to solve it?

module shift8 (
    input      [7:0] A,      // 8-bit vector
    input      [2:0] shamt,  // 3-bit vector
    output reg [7:0] SHL,    // Must be 'reg' for always block
    output reg [7:0] SHR     // Must be 'reg' for always block
);

    // Behavioural block triggers on any change to A or shamt
    always @(*) begin
        SHL = A << shamt;    // Procedural assignment
        SHR = A >> shamt;    // Procedural assignment
    end

endmodule