14. Logical Shifter

How do you plan to solve it?

module shift8 (
    input  [7:0] A,
    input  [2:0] shamt,
    output [7:0] SHL,
    output [7:0] SHR
);

    // TODO: Assign outputs using part-selects and bit-selects
    assign SHL  = A << shamt;
    assign SHR  = A >> shamt;
endmodule