14. Logical Shifter

How do you plan to solve it?

module shift8 (
    input  [7:0] A,
    input  [2:0] shamt,
    output reg [7:0]  SHL,
    output reg [7:0]  SHR
);
always@(*)
begin
     SHL = A << shamt;  // logical left shift (zeros into LSBs)
     SHR = A >> shamt;  // logical right shift (zeros into MSBs)
end
endmodule