14. Logical Shifter

How do you plan to solve it?

module shift8 (
    input  [7:0] A,
    input    [2:0]   shamt,
    output       [7:0] SHL,
    output [7:0] SHR
);

    // Reduction XOR: returns 1 if number of 1s is odd
    assign SHL = A << shamt;

    // Reduction XNOR (or NOT XOR): returns 1 if number of 1s is even
    assign SHR = A>>shamt;

endmodule