14. Logical Shifter

How do you plan to solve it?

module shift8(
input [7:0] A,
input [2:0] shamt,
output reg [7:0] SHL, SHR);
always@(*) begin
if (shamt == 0) begin
    SHL = A;
    SHR = A;
end
else
SHL= A << (shamt);
SHR= A >> (shamt);
end
endmodule