
From Quick Guide:
Multiple Drivers
In real circuits, you can connect multiple outputs to a single wire → in Verilog too, a wire can have multiple drivers.
If drivers conflict:
0 vs 1 → results in x (unknown)
Pull-ups/pull-downs (supply0, supply1) can resolve defaults
When a and b are same, its one value so no conflict hence y gives expected output.
Synthesis Fails as warned in question because of multiple drivers driving single wire.
Synthesis:
4. Executing CHECK pass (checking for obvious problems).
Checking module top_module...
Warning: multiple conflicting drivers for top_module.\b:
module input b[0]
module input a[0]
ERROR: Found 1 problems in 'check -assert'.
/*Write yo-modulur code here*/
module top_module(
input a,
input b,
output y
);
assign y = a;
assign y = b;
endmodule