/*Write yo-modulur code here*/
module top_module(
input a,
input b,
output y
);
assign y = a;
assign y = b;
endmodule
When a abd b both have same vavaales then only y is giving valid output why ?
/*Write yo-modulur code here*/
module top_module(
input a,
input b,
output y
);
assign y = a;
assign y = b;
endmodule