38. Multiplexer Using Primitives

module mux2_prim (
    input  a,
    input  b,
    input  sel,
    output y
);
    wire sel_n, wa, wb;

    not u_inv (sel_n, sel);
    and u_a   (wa, a, sel_n);
    and u_b   (wb, b, sel);
    or  u_or  (y, wa, wb);
endmodule

💡Remember

Gate primitives are structural and follow Verilog’s 4-state tables.
This mux is just two ANDs + one NOT + one OR.
With unknowns: if sel = x, both data paths can be active/inactive → result often x.