Testbench Code

`timescale 1ns/1ps

module tb_mux2_prim;
    // 1) Inputs
    reg a, b, sel;

    // 2) DUT output
    wire y;

    // 3) Expected (prefixed expected_)
    reg expected_y;

    // 4) Mismatch (HIGH on fail) — wire so it never floats 'x'
    wire mismatch = (y !== expected_y);

    // Counters
    integer TOTAL_TEST_CASES        = 0;
    integer TOTAL_PASSED_TEST_CASES = 0;
    integer TOTAL_FAILED_TEST_CASES = 0;

    // VCD limit
    integer VCD_MAX_CASES = 32;

    // DUT
    mux2_prim dut(.a(a), .b(b), .sel(sel), .y(y));

    // VCD dump (Inputs -> Outputs -> Expected -> Mismatch)
    initial begin
        $dumpfile("tb_mux2_prim.vcd");
        $dumpvars(0,
            tb_mux2_prim.a, tb_mux2_prim.b, tb_mux2_prim.sel, // Inputs
            tb_mux2_prim.y,                                   // Output
            tb_mux2_prim.expected_y,                          // Expected
            tb_mux2_prim.mismatch                             // Mismatch
        );
        $dumpon; // start at #0
    end

    // Helper to print 4-state values cleanly
    function [7*8-1:0] bit2s;
        input bitval;
        begin
            if      (bitval === 1'b0) bit2s = "0";
            else if (bitval === 1'b1) bit2s = "1";
            else if (bitval === 1'bx) bit2s = "x";
            else                      bit2s = "z";
        end
    endfunction

    // Apply + check (EXPECTED FIRST -> WAIT -> COMPARE)
    task apply_and_check;
        input ta, tb, tsel;
        begin
            a   = ta; 
            b   = tb; 
            sel = tsel;

            // Expected using 4-state bitwise ops (matches primitive semantics)
            expected_y = ((~tsel & ta) | (tsel & tb));

            #1; // settle DUT

            TOTAL_TEST_CASES++;
            if (!mismatch) TOTAL_PASSED_TEST_CASES++;
            else           TOTAL_FAILED_TEST_CASES++;

            $display(" a=%s b=%s sel=%s | y=%s | exp=%s | mismatch=%0d",
                     bit2s(a), bit2s(b), bit2s(sel),
                     bit2s(y), bit2s(expected_y), mismatch);

            if (TOTAL_TEST_CASES == VCD_MAX_CASES) $dumpoff;
        end
    endtask

    integer i;
    initial begin
        $display(" a b sel | y | expected | mismatch");
        $display("-----------------------------------");

        // Basic 0/1 truth table
        apply_and_check(0,0,0);
        apply_and_check(0,1,0);
        apply_and_check(1,0,0);
        apply_and_check(1,1,0);
        apply_and_check(0,0,1);
        apply_and_check(0,1,1);
        apply_and_check(1,0,1);
        apply_and_check(1,1,1);

        // X/Z corner cases
        apply_and_check(1'bx, 1'b0, 1'b0); // passes a (x)
        apply_and_check(1'b1, 1'bz, 1'b1); // passes b (x)
        apply_and_check(1'b1, 1'b0, 1'bx); // sel=x ->  x
        apply_and_check(1'b0, 1'b1, 1'bx); // sel=x ->  x
        apply_and_check(1'bz, 1'b1, 1'b0); // (x)

        // Summary
        $display("-----------------------------------");
        $display("TOTAL_TEST_CASES=%0d", TOTAL_TEST_CASES);
        $display("TOTAL_PASSED_TEST_CASES=%0d", TOTAL_PASSED_TEST_CASES);
        $display("TOTAL_FAILED_TEST_CASES=%0d", TOTAL_FAILED_TEST_CASES);
        $display("ALL_TEST_CASES_PASSED=%s",
                 (TOTAL_FAILED_TEST_CASES==0) ? "true" : "false");

        #2 $finish;
    end
endmodule