Testbench Code
`timescale 1ns/1ps
module tb_mux8_tree;
// 1) Inputs
reg [7:0] d;
reg [2:0] sel;
// 2) DUT output
wire y;
// 3) Expected
wire expected_y;
// 4) Mismatch (HIGH on fail)
reg mismatch;
wire mismatch_w = (y !== expected_y);
// Counters
integer TOTAL_TEST_CASES=0, TOTAL_PASSED_TEST_CASES=0, TOTAL_FAILED_TEST_CASES=0;
integer VCD_MAX_CASES = 32;
// Seed for reproducible randomness (change to vary runs)
integer seed;
initial seed = 32'h8A1C_F17E ^ $time;
// DUT
mux8_tree dut(.d(d), .sel(sel), .y(y));
// Golden model
assign expected_y = d[sel];
// VCD dump (Inputs -> Outputs -> Expected -> Mismatch)
initial begin
$dumpfile("tb_mux8_tree.vcd");
$dumpvars(0,
tb_mux8_tree.d, tb_mux8_tree.sel, // Inputs
tb_mux8_tree.y, // Output
tb_mux8_tree.expected_y, // Expected
tb_mux8_tree.mismatch // Mismatch
);
$dumpon; // start at #0
end
// Header + init
initial begin
d = 8'b1010_1100; sel = 3'd0; mismatch = 1'b0;
$display(" d sel | y | expected_y | mismatch");
$display("------------------------------------------");
end
// Apply + check
task apply_and_check;
input [7:0] t_d;
input [2:0] t_sel;
begin
d = t_d; sel = t_sel;
#1; // settle
mismatch = mismatch_w;
TOTAL_TEST_CASES++;
if (!mismatch) TOTAL_PASSED_TEST_CASES++; else TOTAL_FAILED_TEST_CASES++;
$display("0x%02h %0d | %1b | %1b | %0d",
d, sel, y, expected_y, mismatch);
if (TOTAL_TEST_CASES == VCD_MAX_CASES) $dumpoff;
end
endtask
integer i;
initial begin
// Directed: sweep sel 0..7 with a fixed visible pattern
d = 8'b1010_1100;
for (i = 0; i < 8; i = i + 1)
apply_and_check(d, i[2:0]);
// A few randomized cases (still well under 32 total)
repeat (8) apply_and_check($random(seed), $random(seed));
// Summary
$display("------------------------------------------");
$display("TOTAL_TEST_CASES=%0d", TOTAL_TEST_CASES);
$display("TOTAL_PASSED_TEST_CASES=%0d", TOTAL_PASSED_TEST_CASES);
$display("TOTAL_FAILED_TEST_CASES=%0d", TOTAL_FAILED_TEST_CASES);
$display("ALL_TEST_CASES_PASSED=%s", (TOTAL_FAILED_TEST_CASES==0) ? "true" : "false");
#2 $finish;
end
endmodule