Problem: AND Gate using NMOS Transistors. Solve this hands-on electronics task on EWskills.

The first stage generates NAND logic. The second stage inverts it. Y = ((A · B)')' = A · B

28. AND Gate using NMOS Transistors

Implement a 2-input AND gate using NMOS transistors so that output Y becomes HIGH only when both inputs are HIGH.

Constraints

Inputs: A, B
Output: Y
Supply: 5 V
Use NMOS transistors and resistors.
Do not use PMOS transistors, BJTs, diodes, switches, or ready-made logic gates.

Behavioral Reference

A	B	Y
0	0	0
0	1	0
1	0	0
1	1	1

Need Help? Refer to the Quick Guide below

Logic gates are physically implemented using transistor switches. A transistor network creates a path either toward the supply or toward ground, producing logic 1 or logic 0.

Note: The circuits shown are simplified for learning; practical IC implementations may use optimized transistor networks.

How Transistors Create Logic

Pull-Up and Pull-Down Paths

Pull-up connects Y toward VCC/VDD → 1.
Pull-down connects Y toward ground → 0.

Series and Parallel Connections

Series: all transistors must be ON. Parallel: any ON branch can complete the path.

Series and Parallel transistor networks.

For resistor-loaded pull-down logic:

series NPN/NMOS → NAND behavior;
parallel NPN/NMOS → NOR behavior.

CMOS uses a complementary pull-up network with the opposite series/parallel arrangement.

Basic Transistor Logic Gates

NOT Gate

Y = A'

NMOS inverter: A = 0 turns the NMOS OFF and the resistor pulls Y=HIGH; A = 1 turns the NMOS ON and pulls Y=LOW. CMOS uses complementary PMOS pull-up and NMOS pull-down devices.

Resistor-loaded NMOS inverter and CMOS inverter.

NAND Gate

Y = (A · B)'

Resistor-loaded NMOS NAND uses two NMOS transistors in series. CMOS NAND uses parallel PMOS devices in the pull-up network and series NMOS devices in the pull-down network.

Resistor-loaded NMOS NAND and CMOS NAND.

NOR Gate

Y = (A + B)'

Resistor-loaded NMOS NOR uses parallel NMOS pull-down branches. CMOS NOR uses series PMOS devices in the pull-up network and parallel NMOS devices in the pull-down network.

Derived Logic Gates

AND Gate

X = (A · B)'   →   Y = X' = A · B

A NAND stage followed by an inverter produces AND.

OR Gate

X = (A + B)'   →   Y = X' = A + B

A NOR stage followed by an inverter produces OR.

Exclusive Logic Gates

XOR Gate

Y = A ⊕ B = A' · B + A · B'

XOR is HIGH when the inputs are different. The shown static CMOS circuit first generates A' and B', then uses complementary pull-up and pull-down paths in the XOR core.

CMOS XOR using an input-inverter stage and complementary XOR core.

XNOR Gate

Y = (A ⊕ B)' = A · B + A' · B'

XNOR is HIGH when the inputs are equal. It can be implemented as a complementary CMOS network or by inverting an XOR output.

CMOS XNOR using complementary input signals and a static CMOS core.

Transistor Logic Families

The same Boolean function can be implemented using different transistor logic families.

Logic Family	Devices Used	Basic Principle
RTL	BJTs + resistors	BJT switching with resistive load
TTL	BJTs	Multiple BJT stages perform logic and active output driving
MOS Logic	NMOS or PMOS + load	One MOSFET type forms the switching network
CMOS	NMOS + PMOS	Complementary pull-up and pull-down networks

RTL Example

In a simple NPN RTL inverter, the resistor pulls Y HIGH when the transistor is OFF, while the NPN transistor pulls Y LOW when it turns ON.

RTL inverter using an NPN transistor and pull-up resistor.

TTL Example

TTL uses BJTs for both logic processing and active output driving. The shown teaching circuit uses separate input transistors Q1A and Q1B, a phase-splitter Q2, and a totem-pole output stage Q3–Q4.

If A = 0 or B = 0, the pull-down output path is not activated and the output is driven HIGH.
If A = 1 and B = 1, Q2 drives the pull-down transistor ON and the output becomes LOW.

Y = (A · B)'

Note: Classic TTL NAND gates normally use a multi-emitter input transistor. This simplified teaching circuit uses separate input transistors to represent the input stage.