5. OR Gate

How do you plan to solve it?

Using the OR binary operand "|" between the inputs on the RHS in a continuous assignment, that will assign the OR result to y on the LHS.

/* OR Gate
 * Inputs: a, b (1-bit each)
 * Output: y (1-bit)
 * Truth Table
 *  a  b | y
 * ----------
 *  0  0 | 0
 *  0  1 | 1
 *  1  0 | 1
 *  1  1 | 1
 */

module top_module (
    input a, b,
    output y
);
    assign y = a | b;

endmodule