5. OR Gate

How do you plan to solve it?

module top_module(input a, input b,output reg y);
always @(*)
begin 
if(a==0 && b==1)
y=1;
else if (a==1 && b==0)
y=1;
else if (a==1 && b==1)
y=1;
else 
y=0;
end
endmodule