Testbench Code

`timescale 1ns/1ps

module tb_parking_status16;
    // Input
    reg  [15:0] slots;

    // DUT outputs
    wire all_full;
    wire any_free;

    // Expected outputs
    reg  expected_all_full;
    reg  expected_any_free;

    // Mismatch signals
    wire mismatch_all_full = (all_full !== expected_all_full);
    wire mismatch_any_free = (any_free !== expected_any_free);
    wire mismatch          = mismatch_all_full | mismatch_any_free;

    integer TOTAL_TEST_CASES = 0;
    integer TOTAL_PASSED_TEST_CASES = 0;
    integer TOTAL_FAILED_TEST_CASES = 0;

    // Instantiate DUT
    parking_status16 dut (
        .slots(slots),
        .all_full(all_full),
        .any_free(any_free)
    );

    // VCD dump (Inputs -> Outputs -> Expected Outputs -> mismatch)
    initial begin
        $dumpfile("tb_parking_status16.vcd");
        $dumpvars(0,
            tb_parking_status16.slots,             // inputs
            tb_parking_status16.all_full,          // outputs
            tb_parking_status16.any_free,
            tb_parking_status16.expected_all_full, // expected
            tb_parking_status16.expected_any_free,
            tb_parking_status16.mismatch           // consolidated mismatch flag
        );
    end

    // Golden model (mirrors reference solution)
    task compute_expected;
        input [15:0] t_slots;
        begin
            expected_all_full = &t_slots;
            expected_any_free = ~(&t_slots);
            // Alternative: expected_any_free = |(~t_slots);
        end
    endtask

    task run_test;
        input [15:0] t_slots;
        begin
            slots = t_slots;
            compute_expected(t_slots);
            #1; // settle
            TOTAL_TEST_CASES = TOTAL_TEST_CASES + 1;

            if (!mismatch) begin
                TOTAL_PASSED_TEST_CASES = TOTAL_PASSED_TEST_CASES + 1;
            end else begin
                TOTAL_FAILED_TEST_CASES = TOTAL_FAILED_TEST_CASES + 1;
                $display("FAILED: slots=%h | all_full=%b any_free=%b | exp_full=%b exp_free=%b mismatch=%b",
                         slots, all_full, any_free, expected_all_full, expected_any_free, mismatch);
            end
        end
    endtask

    integer i;
    initial begin
        // Directed edge/typical cases
        run_test(16'h0000); // all free
        run_test(16'hFFFF); // all full
        run_test(16'hAAAA); // alternating 1010...
        run_test(16'h5555); // alternating 0101...
        run_test(16'h0001); // endpoints occupied only
        run_test(16'hFFFE); // all but endpoints

        // Limited randomized sweep (covers variety but keeps log short)
        for (i = 0; i < 8; i = i + 1)
            run_test($random);

        // Summary
        $display("======================================");
        $display("TOTAL_TEST_CASES=%0d", TOTAL_TEST_CASES);
        $display("TOTAL_PASSED_TEST_CASES=%0d", TOTAL_PASSED_TEST_CASES);
        $display("TOTAL_FAILED_TEST_CASES=%0d", TOTAL_FAILED_TEST_CASES);
        $display("ALL_TEST_CASES_PASSED=%s",
                 (TOTAL_FAILED_TEST_CASES==0) ? "true" : "false");
        $display("======================================");

        $finish;
    end
endmodule