Testbench Code

`timescale 1ns/1ps
module tb_single_driver_line;
  reg  d1, d2;
  wire y;
  wire expected_y;
  wire mismatch;

  single_driver_line dut(.d1(d1), .d2(d2), .y(y));

  assign expected_y = d1;         // only d1 legally drives 'y'
  assign mismatch   = (y !== expected_y);

  integer TOTAL_TEST_CASES, TOTAL_PASSED_TEST_CASES, TOTAL_FAILED_TEST_CASES;
  reg [8*24-1:0] tc_name;

  initial begin
    $dumpfile("tb_single_driver_line.vcd");
    $dumpvars(0, d1, d2, y, expected_y, mismatch);
  end

  task run_case;
    input id1, id2;
    input [8*24-1:0] name;
    begin
      d1 = id1; d2 = id2; tc_name = name; #1;
      $display("CASE=%s : d1=%0b d2=%0b | y=%0b expected_y=%0b %s",
               tc_name, d1, d2, y, expected_y,
               mismatch ? "MISMATCH" : "OK");
      TOTAL_TEST_CASES = TOTAL_TEST_CASES + 1;
      if (!mismatch) TOTAL_PASSED_TEST_CASES = TOTAL_PASSED_TEST_CASES + 1;
      else begin
        TOTAL_FAILED_TEST_CASES = TOTAL_FAILED_TEST_CASES + 1;
        $display("  FAILED INPUTS: d1=%0b d2=%0b  EXPECTED: expected_y=%0b",
                 d1, d2, expected_y);
      end
      #4;
    end
  endtask

  initial begin
    TOTAL_TEST_CASES = 0; TOTAL_PASSED_TEST_CASES = 0; TOTAL_FAILED_TEST_CASES = 0;

    run_case(0,0,"both_zero");
    run_case(1,0,"d1_drives");
    run_case(0,1,"d2_only (ignored)");
    run_case(1,1,"both_one (only d1 matters)");

    $display("TOTAL_TEST_CASES=%0d", TOTAL_TEST_CASES);
    $display("TOTAL_PASSED_TEST_CASES=%0d", TOTAL_PASSED_TEST_CASES);
    $display("TOTAL_FAILED_TEST_CASES=%0d", TOTAL_FAILED_TEST_CASES);
    $display("ALL_TEST_CASES_PASSED=%s", (TOTAL_FAILED_TEST_CASES==0) ? "true" : "false");

    $finish;
  end
endmodule