73. SR Latch

How do you plan to solve it?

module sr_latch_nor (
    input  S,
    input  R,
    output  Q,
    output  Qn
);
reg Q_reg;
    // Write your code here
    always@(*)
    begin
        case({S,R})
        2'b00 : Q_reg <= Q;
        2'b01 : Q_reg <= 0;
        2'b10 : Q_reg <= 1;
        2'b11 : Q_reg <= 1'b0;
        endcase
    end
    assign Q = Q_reg;
    assign Qn = ~Q_reg;
endmodule