73. SR Latch

How do you plan to solve it?

module sr_latch_nor (
    input  S,
    input  R,
    output Q,
    output Qn
);
    wire a,b,c,d;
    not(c,R);
    and(d,S,c);
    nor(a,R,b);
    nor(b,a,d);

    assign Q=a;
    assign Qn=b;
    
endmodule