73. SR Latch

How do you plan to solve it?

module sr_latch_nor (
    input  S,
    input  R,
    output reg Q,
    output reg Qn
);
    // Write your code here
    always@(*)begin
        case({R,S})
            2'b00: begin Q = Q; Qn = ~Q ; end
            2'b01: begin Q = 1; Qn = ~Q ; end
            2'b10: begin Q = 0; Qn = ~Q ; end
            2'b11: begin Q = 0; Qn = ~Q ; end
        endcase
    end

endmodule