73. SR Latch

How do you plan to solve it?

module sr_latch_nor (
    input  S,
    input  R,
    output Q,
    output Qn
);
    reg Q_reg;
    reg Qn_reg;

    // Write your code here
   always @(*) begin
    if (S == 1 && R == 0) begin
        Q_reg = 1'b1; Qn_reg = 1'b0;
    end
    else if (S == 0 && R == 1) begin
        Q_reg = 1'b0; Qn_reg = 1'b1;
    end else if (S == 0 && R == 0) begin
        Q_reg = Q;
    end
    else begin
        Q_reg  = 1'b0;
        Qn_reg = 1'b1;
    end
    end
    assign Q  = Q_reg;
    assign Qn = Qn_reg;
endmodule