73. SR Latch

How do you plan to solve it?

module sr_latch_nor (
    input  S,
    input  R,
    output reg Q,   // level-sensitive storage
    output Qn
);

    // Level-sensitive SR latch behavior
    always @(*) begin
        case ({S, R})
            2'b10: Q = 1'b1;      // S=1, R=0 → Set
            2'b01: Q = 1'b0;      // S=0, R=1 → Reset
            2'b11: Q = 1'b0;      // S=1, R=1 → treated as Reset (deterministic)
            2'b00: ;              // S=0, R=0 → Hold (no assignment → latch)
            default: ;            // safety
        endcase
    end

    // Qn is always logical complement of Q
    assign Qn = ~Q;

endmodule