73. SR Latch

How do you plan to solve it?

module sr_latch_nor (
    input  S,
    input  R,
    output Q,
    output Qn
);
    reg Q_reg;
    // Write your code here
    always @(*) begin
        Q_reg = (1'b0 | ~R) & ( S | Q_reg );
    end

    assign Q = Q_reg;
    assign Qn = ~Q;
    
endmodule