73. SR Latch

How do you plan to solve it?

module sr_latch_nor (
    input  S,
    input  R,
    output Q,
    output Qn
);
    reg Q_reg;

    always @(*) begin
        if (S && !R) begin
            Q_reg = 1'b1;        // SET
        end 
        else if (!S && R) begin
            Q_reg = 1'b0;        // RESET
        end 
        else if (S && R) begin
            Q_reg = 1'b0;        // illegal → RESET (as per requirement)
        end
        // else (S=0, R=0) → HOLD → no assignment
    end

    assign Q  = Q_reg;
    assign Qn = ~Q_reg;

endmodule