73. SR Latch

How do you plan to solve it?

module sr_latch_nor (
    input  S,
    input  R,
    output reg Q,
    output Qn
);

assign Qn = ~Q;

always @(*) begin
    case ({S, R})
        2'b10: Q <= 1;
        2'b01: Q <= 0;
        2'b11: Q <= 0;
    endcase
end

endmodule