73. SR Latch

How do you plan to solve it?

module sr_latch_nor (
    input  S,
    input  R,
    output reg Q,
    output reg Qn
);

    // Combinational logic for SR latch
    always @(*) begin
        case ({S, R})
            2'b10: begin 
                Q = 1;    // Set Q to 1
                Qn = 0;   // Set Qn to 0
            end
            2'b01: begin 
                Q = 0;    // Set Q to 0
                Qn = 1;   // Set Qn to 1
            end
            2'b00: begin 
                // Maintain the current state (no change)
                Q = Q;    
                Qn = Qn;
            end
            2'b11: begin 
                // Invalid state: Retain previous state (or undefined behavior)
                Q = 0;    // Retain previous state (memory latch)
                Qn = 1;  // Retain previous state (memory latch)
            end
        endcase
    end
    
endmodule