73. SR Latch

How do you plan to solve it?

module sr_latch_nor (
    input  S,
    input  R,
    output Q,
    output Qn
);
    // Write your code here

    reg q_r, qn_r ; // to save the Q and Qn state
    
    always @(*) begin

        if(R==1 && S==0)begin
            q_r   = 0;
            qn_r = 1;
        end

        else if(R==0 && S==1)begin
            q_r   = 1;
            qn_r  = 0;
        end

        else if(R==1 && S==1)begin
            q_r   = 0;
            qn_r  = 1;
        end


        else if(R==0 && S==1)begin
            q_r   = 1;
            qn_r  = 0;
        end

        else if(R==0 && S==0)begin
            q_r   = Q;
            qn_r  = Qn;
        end        

    end

    assign Q  = q_r;
    assign Qn = qn_r;
    
endmodule