73. SR Latch

How do you plan to solve it?

module sr_latch_nor (
    input  wire S,
    input  wire R,
    output reg  Q,
    output reg  Qn
);

    always @(*) begin
        // Reset (R dominates, including S=1,R=1 case)
        if (R) begin
            Q  = 1'b0;
            Qn = 1'b1;
        end
        // Set
        else if (S) begin
            Q  = 1'b1;
            Qn = 1'b0;
        end
    end

endmodule