73. SR Latch

How do you plan to solve it?

module sr_latch_nor (
    input  S,
    input  R,
    output Q,
    output Qn
);
    wire not_r,and_s_not_r;
    not n1(not_r,R);
    and a1(and_s_not_r,not_r,S);
    nor xn1(Q,Qn,R);
    nor xn2(Qn,Q,and_s_not_r);
endmodule